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| M62393P/FP 8-bit 8ch I2C BUS D/A Converter with Buffer Amplifiers REJ03D0884-0300 Rev.3.00 Mar 25, 2008 Description The M62393P/FP is an integrated circuit semiconductor of CMOS structure with 8 channels of built-in D/A converters with output buffer operational amplifiers. The input is 2-wires serial method is used for the transfer format of digital data to allow connection with a microcomputer with minimum wiring. The output buffer operational amplifier employs AB class output circuit with sink and source drive capacity of 1.0 mA or more, and it operates in the whole voltage range from VrefU to ground. And because of connects maximum 8 pieces to 64 channels control. Features * Digital data transfer format: I2C BUS serial data method * Output buffer operational amplifier It operates in the whole voltage range from VrefU (0 to 5 V) to ground. * High output current drive capacity: 1.0 mA over * Preparation two high level reference voltage terminal because there are two high level reference voltage terminal, it can set up two kinds differ voltage range. Application Conversion from digital control data to analog control data for home-use and industrial equipment. Signal gain control or automatic adjustment of display-monitor or CTV. Block Diagram CS0 CS1 CS2 20 19 18 VDD 17 AO4 15 AO3 14 AO2 13 AO1 12 VCC 16 VrefU 2 11 Chip select + - + - + - + - I2C BUS transceiver Address decoder 8-bit upper segment R-2R 8-bit upper segment R-2R 8-bit upper segment R-2R 8-bit upper segment R-2R 8-bit latch 8-bit latch 8-bit latch 8-bit latch 8 8-bit latch 8-bit upper segment R-2R 8-bit latch 8-bit upper segment R-2R 8-bit latch 8-bit upper segment R-2R 8-bit latch 8-bit upper segment R-2R + - + - + - + - 1 R 2 SCL 3 SDA 8 VrefL 4 AO5 5 AO6 6 AO7 7 AO8 10 GND 9 VrefU1 REJ03D0884-0300 Rev.3.00 Mar 25, 2008 Page 1 of 6 M62393P/FP Pin Arrangement M62393P/FP R SCL SDA AO5 AO6 AO7 AO8 VrefL VrefU1 GND 1 2 3 4 5 6 7 8 9 10 20 CS0 19 CS1 18 CS2 17 VDD 16 VCC 15 AO4 14 AO3 13 AO2 12 AO1 11 VrefU2 (Top view) Outline: 20P4 PRSP0020DA-A (20P2N-A) Pin Description Pin No. 3 1 2 12 13 14 15 4 5 6 7 16 17 10 8 9 11 18 19 20 Pin Name SDA R SCL Ao1 Ao2 Ao3 Ao4 Ao5 Ao6 Ao7 Ao8 VCC VDD GND VrefL VrefU1 VrefU2 CS2 CS1 CS0 Function Serial data input terminal Reset signal input terminal Serial clock input terminal 8-bit D/A converter output terminal Analog power supply terminal Digital power supply terminal Analog and digital common GND D/A converter low level reference voltage input terminal D/A converter high level reference voltage input terminal 1 D/A converter high level reference voltage input terminal 2 Chip select data input terminal 2 Chip select data input terminal 1 Chip select data input terminal 0 REJ03D0884-0300 Rev.3.00 Mar 25, 2008 Page 2 of 6 M62393P/FP Absolute Maximum Ratings Item Supply voltage Supply voltage D/A converter high level reference voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Symbol VCC VDD VrefU1, 2 VIN VO Pd Topr Tstg Ratings -0.3 to +7.0 -0.3 to +7.0 -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 990 (P) / 590 (FP) -20 to +85 -40 to +125 Unit V V V V V mW C C Electrical Characteristics Item Supply voltage Supply current Output low voltage (SDA) Input leak current Input low voltage Input high voltage Symbol VDD IDD VOL IILK VIL VIH Min 4.5 -- -- -10 -- 0.8 VCC Limits Typ 5.0 -- -- -- -- -- Max 5.5 1.0 0.4 10 0.2 VCC -- Unit V mA V A V V Conditions CLK = 1 MHz operation, IAO = 0 A Isink = 3 mA VIN = 0 to VCC Item Supply voltage Supply current D/A converter high level reference voltage input current D/A converter high level reference voltage range D/A converter low level reference voltage range Buffer amplifier output voltage range Buffer amplifier output current range Differential nonlinearity Nonlinearity Zero code error Full scale error Output capacitive load Buffer amplifier output impedance Symbol VCC ICC IrefU Min 4.5 -- -- Limits Typ 5.0 1.6 1.0 Max 5.5 3.2 2.0 Unit V mA mA Conditions CLK = 1 MHz operation, IAO = 0 A VrefU = 5 V, VrefL = 0 V Data condition: at maximum current The output dose not necessarily be the values within the reference voltage setting range. IAO = 100 A IAO = 500 A Upper side saturation voltage = 0.3 V Lower side saturation voltage = 0.2 V VrefU = 4.79 V VrefL = 0.95 V VCC = 5.5 V (15 mV/LSB) Without load (IAO = 0) VrefU VrefL VAO IAO SDL SL SZERO SFULL CO RO 3.5 GND 0.1 0.2 -1.0 -1.0 -1.5 -2.0 -2.0 -- -- -- -- -- -- -- -- -- -- -- -- 5.0 VCC VCC - 3.5 VCC - 0.1 VCC - 0.2 1.0 1.0 1.5 2.0 2.0 0.1 -- V V V V mA LSB LSB LSB LSB F REJ03D0884-0300 Rev.3.00 Mar 25, 2008 Page 3 of 6 M62393P/FP I2C BUS Line Characteristics Item SCL clock frequency Time the bus must be free before a new transmission can start Hold time start condition. After this period. The first clock pulse is generated. Low period of the clock High period of the clock Setup time for start condition (only relevant for a repeated start condition) Hold time data Setup time data Rise time of both SDA and SCL lines Fall time of both SDA and SCL lines Setup time for stop condition Note: Symbol fSCL tBUF tHD : STA tLOW tHIGH tSU : STA tHD : DAT tSU : DAT tR tF tSU : STO Normal Mode Min Max 0 4.7 4.0 4.7 4.0 4.7 0 250 -- -- 4.0 100 -- -- -- -- -- -- -- 1000 300 -- High Speed Mode Min Max 0 1.3 0.6 1.3 0.6 4.7 0 100 20 20 0.6 400 -- -- -- -- -- 0.9 -- 300 300 -- Unit kHz s s s s s s ns ns ns s Transmitter must internally at reset a hold time to bridge the undefined region (300 ns Max) of the falling edge of SCL. Timing Chart tr, tf tBUF VIH SDA VIL tHD:STA tSU:DAT tHD:DAT tSU:STA tSU:STO VIH SCL VIL tLOW tHIGH Start Start Stop Start REJ03D0884-0300 Rev.3.00 Mar 25, 2008 Page 4 of 6 M62393P/FP I2C BUS Format STA Slave address W A Sub address A DAC data A STP Digital Data Format * Slave Address First 1 0 0 1 A2 A1 Last A0 * Sub Address First X X X X S3 S2 S1 Last S0 (Slave address) Chip select data Don't care Last LSB Channel select data * DAC Data First MSB D7 D6 D5 D4 D3 D2 D1 D0 (1) Chip Select Data MSB A2 0 0 0 : 1 A1 0 0 1 : 1 LSB A0 0 1 0 : 1 CS2 0 0 0 : 1 CS1 0 0 1 : 1 CS0 0 1 0 : 1 (2) Channel Select Data MSB S3 0 0 0 : 0 1 1 : 1 S2 0 0 0 : 1 0 0 : 1 S1 0 0 1 : 1 0 0 : 1 LSB S0 0 1 0 : 1 0 1 : 1 Channel Selection Don't care ch1 selection ch2 selection : ch7 selection ch8 selection Don't care : Don't care (3) DAC Data First MSB D7 0 0 0 0 : 1 1 D6 0 0 0 0 : 1 1 D5 0 0 0 0 : 1 1 D4 0 0 0 0 : 1 1 D3 0 0 0 0 : 1 1 D2 0 0 0 0 : 1 1 D1 0 0 1 1 : 1 1 Last LSB D0 0 1 0 1 : 0 1 DAC Output (VrefU - VrefL ) / 256 x 1 + VrefL (VrefU - VrefL ) / 256 x 2 + VrefL (VrefU - VrefL ) / 256 x 3 + VrefL (VrefU - VrefL ) / 256 x 4 + VrefL : (VrefU - VrefL ) / 256 x 255 + VrefL VrefU REJ03D0884-0300 Rev.3.00 Mar 25, 2008 Page 5 of 6 M62393P/FP Package Dimensions 20P4 EIAJ Package Code DIP20-P-300-2.54 JEDEC Code -- Weight(g) 1.3 Lead Material Alloy 42/Cu Alloy Plastic 20pin 300mil DIP 20 11 1 10 D Symbol A A1 A2 b b1 b2 c D E e e1 L SEATING PLANE LA A1 e b1 b b2 Dimension in Millimeters Min Nom Max 4.5 -- -- 0.51 -- -- 3.3 -- -- 0.4 0.5 0.6 1.4 1.5 1.8 0.9 1.0 1.3 0.22 0.27 0.34 23.8 24.0 24.2 6.15 6.3 6.45 2.54 -- -- 7.62 -- -- 3.0 -- -- 0 15 -- JEITA Package Code P-SOP20-5.3x12.6-1.27 RENESAS Code PRSP0020DA-A Previous Code 20P2N-A MASS[Typ.] 0.3g 20 11 HE *1 E F A2 1 Index mark 10 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. c *2 D A2 A1 Reference Symbol e1 Dimension in Millimeters Detail F E c *3 e bp y D E A2 A1 A bp c HE e y L Min Nom Max 12.5 12.6 12.7 5.2 5.3 5.4 1.8 0.1 0.2 0 2.1 0.35 0.4 0.5 0.18 0.2 0.25 0 8 7.5 7.8 8.1 1.12 1.27 1.42 0.1 0.4 0.6 0.8 A REJ03D0884-0300 Rev.3.00 Mar 25, 2008 Page 6 of 6 L Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. 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